Electrostatic discharge (ESD) protection circuits are utilized to protect input and output circuitry from ESD as taught in prior art U.S. Pat. No. 5,268,588, U.S. Pat. No. 4,896,243, U.S. Pat. No. 5,077,591, U.S. Pat. No. 5,060,037, U.S. Pat. No. 5,012,317, U.S. Pat. No. 5,225,702 and U.S. Pat. No. 5,290,724 all assigned to Texas Instruments, Inc.
Many ESD protection circuits utilize a two stage protection scheme on circuit inputs as shown in prior art FIG. 1. Typically the high current pulse of an ESD strike passes through the primary clamp which clamps the pad voltage. However this is still too high a voltage for the circuitry to receive, therefore the secondary clamp clamps the voltage to a safe value. The current limit structure limits the current so that the secondary clamp does not have to be excessively large.
As complimentary oxide semiconductor (CMOS) processes evolve to transistor shorter channel lengths and thinner gate oxides, it becomes more difficult to protect both input and output circuits from damage due to ESD. For example, as the gate oxide of transistors become thinner, the breakdown voltage of the gate oxide will become lower than the breakdown voltages of the standard CMOS process flow diffusions. Therefore the standard prior art ESD clamps will no longer protect the gate oxide from ESD because the gate oxide will fail before the ESD clamp begins to clamp the ESD pulse.
Prior art primary clamps also suffer from limitations. They exhibit high clamping voltages that provide little headroom for "IR" drops that occur in electrostatic discharge protection circuits due to the large currents and small metallization resistance. A primary clamp circuit that could clamp ESD pulses at lower voltage levels would be beneficial.
Output circuits also suffer from low ESD level damage. If the output device evenly breaks down it absorbs the ESD energy. However, the output device may not turn on completely or evenly, but rather will conduct in localized areas at a voltage value lower than the device breakdown. When this occurs, a "hot spot" is created and the device suffers damage.
It is an object of this invention to provide an ESD protection circuit that protects both circuit inputs and outputs from ESD. Other objects and advantages of the invention will become apparent to those of ordinary skill in the art having reference to the following specification together with the drawings herein.